The present invention relates to a MOS (Metal Oxide Semiconductor) transistor circuit and a semiconductor integrated circuit. The present invention relates, in particular, to a MOS transistor circuit and a semiconductor integrated circuit suitable for lower power consumption.
Along with the increased degree of integration of a large scale integrated circuit (LSI) and its higher-speed operation in recent years, there is a problem of higher LSI power consumption and thus power reduction is strongly required. Since the LSI power consumption is proportional to square of a power supply voltage, reducing the power supply voltage is effective to reduce power consumption. However, if only the power supply voltage is reduced, high-speed operation is disabled due to lower on-currents of a MOS transistor. To avoid this problem, the absolute value of the threshold voltage of the MOS transistor needs to be lowered as the power supply voltage is reduced. However, if the absolute value of the threshold voltage is lowered, the off-currents are increased by subthreshold currents of the MOS transistor.
As disclosed in Japanese Patent Publication No. Hei 8-12917, a method of controlling the threshold voltage of the MOS transistor with the voltage of a gate terminal by connecting a semiconductor substrate or well with which the MOS transistor is formed to the gate terminal is proposed as a MOS transistor circuit for relieving the problem of increased off-currents. That is, the semiconductor substrate or well with which an NMOS transistor 1 is formed and the gate terminal of the NMOS transistor 1 are connected as shown in FIG. 6. When a voltage at which the NMOS transistor 1 is turned on (that is, a voltage which is positive relative to a source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well. Therefore, the absolute value of the threshold voltage is equivalently reduced and thereby the on-current increases. On the other hand, when a voltage at which the NMOS transistor 1 is turned off (that is, a voltage which is equal or negative relative to the source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well. Therefore, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced.
For example, the relationship between gate voltages Vgs of the NMOS transistor 1 and drain currents Ids can be set as shown in FIG. 7. The on-current can be increased to 10xe2x88x924 A/xcexcm, which is the same level as that of a usual MOS transistor having a low-threshold voltage, while the off-current can be reduced to 10xe2x88x9210 A/xcexcm as in the case of a usual MOS transistor having a high-threshold voltage.
It is noted that, although an NMOS transistor is exemplified in FIG. 6, this configuration is also applicable to a PMOS transistor. That is, when a voltage at which a PMOS transistor is turned on (that is, a voltage which is negative relative to the source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well with which the PMOS transistor is formed. Therefore, the absolute value of the threshold voltage is equivalently reduced and thereby the on-current increases. On the other hand, when a voltage at which the PMOS transistor is turned off (that is, a voltage which is equal or positive relative to the source voltage Vs) is applied as a gate voltage Vg, the same voltage is applied to the semiconductor substrate or well. Therefore, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced.
A configuration shown in FIG. 8 is obtained when a CMOS (complementary metal oxide semiconductor) inverter circuit is constituted by using MOS transistors formed with a semiconductor substrate or well connected to a gate terminal as described above. To simplify the description below, it will be assumed that both a PMOS transistor 3 and an NMOS transistor 4 have characteristics shown in FIG. 7. The semiconductor substrate or well with which the PMOS transistor 3 and the NMOS transistor 4 are formed is connected to gate terminals of the PMOS transistor 3 and the NMOS transistor 4 (that is, an input terminal 5 of the CMOS inverter circuit). Voltages Vsubp, Vsubn of the semiconductor substrate or well are equal to the voltage Vin of the input terminal 5.
Therefore, since a turn-on voltage is applied to the PMOS transistor 3 when the voltage Vin of the input terminal 5 is equal to the ground voltage Gnd, the absolute value of the threshold voltage is equivalently lowered and the on-current is increased to 10xe2x88x924 A/xcexcm. Since a turn-off voltage is applied to the NMOS transistor 4 at the same time, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced to 10xe2x88x9210 A/xcexcm. On the other hand, since a turn-off voltage is applied to the PMOS transistor 3 when the voltage Vin of the input terminal 5 is equal to the power supply voltage Vdd, the absolute value of the threshold voltage is equivalently increased and thereby the off-current is reduced to 10xe2x88x9210 A/xcexcm. Since a turn-on voltage is applied to the NMOS transistor 4 at the same time, the absolute value of the threshold voltage is equivalently lowered and the on-current is increased to 10xe2x88x924 A/xcexcm. Thus, the on-current of the PMOS transistor 3 or the NMOS transistor 4 turned on becomes 10xe2x88x924 A/xcexcm and the driving current of the CMOS inverter circuit is increased to 10xe2x88x924 A/xcexcm. The off-current of the NMOS transistor 4 or the PMOS transistor 3 turned off becomes 10xe2x88x9210 A/xcexcm and thereby the leakage current flowing from the power supply voltage terminal to the ground voltage terminal is reduced to 10xe2x88x9210 A/xcexcm.
As disclosed in Japanese Patent Laid-Open Publication No. 5-108194 as another MOS transistor circuit for relieving the problem of increased off-current, it is proposed that LSI is in an active state that switching operation is performed or a standby state that switching operation is not performed and that the absolute value of the threshold voltage of a MOS transistor is set to be low in the active state and high in the standby state.
In this case, the threshold voltage is switched by switching the voltage Vsub of a semiconductor substrate or well with which an NMOS transistor 11 is formed as shown in FIG. 9. 12 denotes a select circuit. Vact is selected by a Select signal in an active state while Vstb is selected and outputted as Vsub in a standby state. In this case, if the voltage Vact and the voltage Vstb are set as Vact greater than Vstb, the absolute value of the threshold voltage of the NMOS transistor 11 is higher when the voltage Vstb is applied as Vsub than when voltage Vact is applied. By doing this, for example, the relationship between gate voltages Vgs and drain currents Ids of the NMOS transistor 11 can be set as shown in FIG. 10. The on-current in the active state can be increased to 10xe2x88x924 A/xcexcm while the off-current in the standby state can be reduced to 10xe2x88x9212 A/xcexcm.
It is noted that, although an NMOS transistor is exemplified in FIG. 9, but this configuration is also applicable to a PMOS transistor. That is, in the case of a PMOS transistor, if the voltage Vact and the voltage Vstb are set as Vact less than Vstb, the absolute value of the threshold voltage of the PMOS transistor 11 is higher when the voltage Vstb is applied as the voltage Vsub of the semiconductor substrate or well than when the voltage Vact is applied.
The configuration shown in FIG. 11 is obtained when a CMOS (complementary metal oxide semiconductor) inverter circuit is constituted by using MOS transistors capable of switching voltages of a semiconductor substrate or well as described above. To simplify the description below, it will be assumed that both a PMOS transistor 13 and an NMOS transistor 14 have characteristics shown in FIG. 10. The threshold voltages of the PMOS transistor 13 and the NMOS transistor 14 are switched by switching the voltages Vsubp, Vsubn of the semiconductor substrate or well with which the PMOS transistor 3 and the NMOS transistor 4 are formed. Select circuits 15, 16 select Vactp, Vactn by a Selectp signal and Selectn signal, respectively, in an active state or Vstbp and Vstbn in a standby state so as to be outputted as the voltages Vsubp, Vsubn of the semiconductor substrate or well. In this case, if the voltages Vactp, Vstbp, Vactn and Vstbn are set as Vactp less than Vstbp and Vactn greater than Vstbn, the absolute values of the threshold voltages of the PMOS transistor 13 and the NMOS transistor 14 are lowered in the active state. Therefore, the on-current of the PMOS transistor 13 or the NMOS transistor 14 turned on becomes 10xe2x88x924 A/xcexcm and the driving current of the CMOS inverter circuit is increased to 10xe2x88x924 A/xcexcm. On the other hand, the absolute values of the threshold voltages of the PMOS transistor 13 and the NMOS transistor 14 are increased in the standby state. Therefore, the off-current of the NMOS transistor 14 or the PMOS transistor 13 turned off becomes 10xe2x88x9212 A/xcexcm and thereby the leakage current flowing from the power supply voltage terminal to the ground voltage terminal is reduced to 10xe2x88x9212 A/xcexcm.
However, there are problems described below with the above-described conventional MOS transistor circuit where the semiconductor substrate or well is connected to the gate terminal (hereinafter, referred to as a first conventional circuit) and the MOS transistors capable of switching voltages of the semiconductor substrate or well (hereinafter, referred to as a second conventional circuit).
That is, a first conventional circuit having a structure shown in FIG. 6 increases the on-current while reducing the off-current. The off-current is 10xe2x88x9210 A/xcexcm as shown in FIG. 7. This is higher than 10xe2x88x9212 A/xcexcm, which is the off-current in a standby state in a second conventional circuit (FIG. 10). Since the first conventional circuit cannot sufficiently suppress leakage currents in the standby state, this circuit cannot be used for equipment such as a mobile phone, a hand-held terminal or the like where leakage currents in the standby state need to be suppressed.
The second conventional circuit having a structure shown in FIG. 9 reduces only leakage currents in the standby state. Although the off-current in the standby state is as low as 10xe2x88x9212 A/xcexcm as shown in FIG. 10, the off-current in the active state is as high as 10xe2x88x928 A/xcexcm. Therefore, when a CMOS circuit such as a CMOS inverter circuit shown FIG. 11 or the like is constituted, there is a problem that leakage currents from the power supply voltage terminal to the ground voltage terminal in the active state become very high. Particularly, if the power supply voltage is reduced along with further miniaturization, leakage currents increase in response to discharge/charge currents. Power consumption increased by the leakage currents in the active state becomes a serious problem.
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit which can increase on-currents and reduce off-currents in an active state and further reduce the off-currents in the standby state or a semiconductor integrated circuit which can increase on-currents and reduce off-currents regardless of whether the circuit is in the active state or the standby state.
In order to achieve the above object, there is provided a MOS transistor circuit comprising: switching means for electrically switching a connection of a semiconductor substrate or well with which a MOS transistor is formed to either a gate terminal of the MOS transistor or a substrate voltage terminal for the semiconductor substrate or well.
According to the above constitution, connections of the semiconductor substrate or well with which the MOS transistor is formed are electrically switched between the gate terminal of the MOS transistor and the substrate voltage terminal for the semiconductor substrate or well by the switching means. Thus, the threshold voltage of the MOS transistor is controlled by both the voltage of the gate terminal and the voltage of the substrate voltage terminal. Therefore, the on-current can be increased and the off-current can be reduced by setting the voltage of the gate terminal and the substrate voltage terminal properly.
In one embodiment of the present invention, when the MOS transistor is a first MOS transistor, the switching means are constituted by: a second MOS transistor whose source and drain terminals are connected to the semiconductor substrate or well and a gate terminal, and a third MOS transistor whose source and drain terminals are connected to the semiconductor substrate or well and a substrate voltage terminal.
According to the above constitution, when the second MOS transistor is turned on, the semiconductor substrate or well is connected to the gate terminal and the threshold voltage of the MOS transistor is controlled by the voltage of the gate terminal. On the other hand, when the third MOS transistor is turned on, the semiconductor substrate or well is connected to the substrate voltage terminal and the threshold voltage of the MOS transistor is controlled by the voltage of the substrate voltage terminal. By controlling an ON/OFF state of the second and third MOS transistors, a medium for controlling the threshold voltages of the MOS transistors can be switched between the voltage of the gate terminal and the voltage of the substrate voltage terminal. Thus, the configuration of the switching means can be simplified to prevent the increase in the circuit scale.
In one embodiment of the present invention, the MOS transistor connected to a terminal having a lower potential out of the gate terminal and the substrate voltage terminal out of the second MOS transistor and the third MOS transistor is an n-type MOS transistor, and the MOS transistor connected to a terminal having a higher potential out of the gate terminal and the substrate voltage terminal out of the second MOS transistor and the third MOS transistor is a p-type MOS transistor.
According to the above constitution, there is no voltage increase or voltage drop by the threshold voltages of the second MOS transistor and the third MOS transistor constituting the switching means. Therefore, the voltage of the substrate or well of the first MOS transistor becomes equal to the voltage of the gate terminal or the substrate voltage terminal. Therefore, the threshold voltage of the first MOS transistor can be efficiently controlled.
In one embodiment of the present invention, the switching means switches a connection in response to a switching signal, and the gate terminal of the second MOS transistor and the gate terminal of the third MOS transistor are connected to a switching signal input terminal for the switching signal.
According to the above constitution, ON/OFF states of the second MOS transistor and the third MOS transistor constituting the switching means are controlled by one switching signal from the switching signal input terminal.
In one embodiment of the present invention, the absolute value of the threshold voltage of the second MOS transistor and that of the third MOS transistor are higher than the absolute value of the threshold voltage of the first MOS transistor.
According to the above constitution, even if a voltage higher than that of the first MOS transistor is applied to the second MOS transistor or the third MOS transistor constituting the switching means, leakage currents through the second MOS transistor and the third MOS transistor can be suppressed to a low level.
In one embodiment of the present invention, the switching means switches a connection in response to switching of the MOS transistor circuit between an active state and a standby state.
According to the above constitution, switching by the switching means is performed in response to switching between the active state and the standby state of the MOS transistor circuit. The absolute value of the threshold voltage of the first MOS transistor is set to be a voltage suitable for the active state or the standby state.
In one embodiment of the present invention, the switching means switches a connection so that the semiconductor substrate or well is electrically connected to the gate terminal in the active state while the semiconductor substrate or well is electrically connected to the substrate voltage terminal in the standby state.
According to the above constitution, the threshold voltage of the MOS transistor is controlled by the voltage of the gate terminal in the active state so that the on-current is increased and the off-current is reduced. On the other hand, the threshold voltage of the MOS transistor is controlled by the voltage of the substrate voltage terminal in the standby state. The off-current can be controlled by the voltage of the substrate voltage terminal so as to be further reduced compared with that in the active state.
In one embodiment of the present invention, the switching means switches a connection in response to the change in a gate voltage of the MOS transistor.
According to the above constitution, switching of connections by the switching means is performed in response to the change in the gate voltage of the MOS transistor and the threshold voltage of the MOS transistor is set to be a voltage suitable as a gate voltage.
In one embodiment of the present invention, the switching means switches a connection so that the semiconductor substrate or well is electrically connected to the gate terminal when the gate voltage is a voltage at which the MOS transistor conducts while the semiconductor substrate or well is electrically connected to the substrate voltage terminal when the gate voltage is a voltage at which the MOS transistor does not conduct.
According to the above constitution, when the MOS transistor is conducting, the absolute value of the threshold voltage of the MOS transistor is controlled by the voltage of the gate terminal so as to be lowered and thereby the on-current is increased. On the other hand, when the MOS transistor is not conducting, the absolute value of the threshold voltage can be controlled by the voltage of the substrate voltage terminal so as to be increased.
In one embodiment of the present invention, the voltage of the substrate voltage terminal is a voltage at which the absolute value of the threshold voltage of the MOS transistor is increased when the semiconductor substrate or well is electrically connected to the substrate voltage terminal.
According to the above constitution, when the semiconductor substrate or well with which the MOS transistor is formed is electrically connected to the substrate voltage terminal, the absolute value of the threshold voltage of the MOS transistor is increased. Therefore, the off-current is reduced by connecting the substrate or well to the substrate voltage terminal in a standby state or a non-conductive state.
Also, there is provided a CMOS logic circuit using the MOS transistor circuit comprising: a first MOS transistor circuit where the MOS transistor is a p-type MOS transistor, and a second MOS transistor circuit where the MOS transistor is an n-type MOS transistor.
According to the above constitution, when the semiconductor substrate or well with which the PMOS transistor of the first MOS transistor circuit and the NMOS transistor of the second MOS transistor circuit are formed is connected to the gate terminals in the active state while connected to the substrate voltage terminals in the standby state, the driving current is increased and leakage currents are reduced in the active state and leakage currents can be further reduced in the standby state. When either the semiconductor substrate or well of the PMOS transistor or the semiconductor substrate or well of the NMOS transistor is connected to the gate terminal and the other is connected to the substrate voltage terminal, the driving current can be increased while leakage currents are reduced regardless of whether the circuit is in the active state or the standby state.
In one embodiment of the present invention, the semiconductor substrate or well with which the p-type MOS transistor constituting first switching means, which is means for switching the first MOS transistor circuit, is formed is connected to a first substrate voltage terminal, which is a substrate voltage terminal of the first MOS transistor circuit, while the semiconductor substrate or well with which the n-type MOS transistor constituting the first switching means is formed is connected to a ground voltage terminal, and the semiconductor substrate or well with which the p-type MOS transistor constituting second switching means, which is means for switching the second MOS transistor circuit, is formed is connected to a power supply voltage terminal while the semiconductor substrate or well with which the n-type MOS transistor constituting the second switching means is formed is connected to a second substrate voltage terminal, which is a substrate voltage terminal of the second MOS transistor circuit.
According to the above constitution, the voltage of the substrate or well of respective PMOS transistors constituting the first switching means for the first MOS transistor circuit and the second switching means for the second MOS transistor circuit becomes equal to the voltage of the source terminal or higher while the voltage of the substrate or well of respective NMOS transistors constituting the two switching means becomes equal to the voltage of the source terminal or lower. Thus, the absolute value of the threshold voltages of the PMOS transistor and the NMOS transistor constituting the two switching means are increased and thereby the leakage currents through the respective MOS transistors constituting the two switching means can be suppressed to a low level.
In one embodiment of the present invention, the semiconductor substrate or well with which the p-type MOS transistor constituting the first switching means, which is means for switching the first MOS transistor circuit is formed is connected to the first substrate voltage terminal, which is a substrate voltage terminal of the first MOS transistor circuit, while the semiconductor substrate or well with which the n-type MOS transistor constituting the first switching means is formed is connected to the second substrate voltage terminal, which is a substrate voltage terminal of the second MOS transistor circuit, and the semiconductor substrate or well with which the p-type MOS transistor constituting the second switching means, which is means for switching the second MOS transistor circuit, is formed is connected to the first substrate voltage terminal while the semiconductor substrate or well with which the n-type MOS transistor constituting the second switching means is formed is connected to the second substrate voltage terminal.
According to the above constitution, the voltage of the substrate or well of the NMOS transistor constituting the first switching means is made lower than in the case of being connected to the ground voltage terminal. Further, the voltage of the substrate or well of the PMOS transistor constituting the second switching means is made higher than in the case of being connected to the power supply voltage terminal. Thus, the absolute value of the threshold voltage of the respective MOS transistors constituting the two switching means is further increased and thereby the leakage currents through the respective MOS transistors are further reduced.
In one embodiment of the present invention, a first switching signal input terminal, which is a switching signal input terminal for the first MOS transistor circuit, and a second switching signal input terminal, which is a switching signal input terminal for the second MOS transistor circuit, are connected.
According to the above constitution, switching connections of the first switching means for the first MOS transistor circuit and the second switching means for the second MOS transistor circuit is controlled by one switching signal.
In one embodiment of the present invention, the switching signal is generated by a p-type MOS transistor where source and drain terminals thereof are connected to the first switching signal input terminal and the second switching signal input terminal and the first substrate voltage terminal, which is a substrate voltage terminal of the first MOS transistor circuit, while a gate terminals is connected to an input terminal of the CMOS logic circuit and
an n-type MOS transistor where source and drain terminals are connected to the first switching signal input terminal and the second switching signal input terminal and the second substrate voltage terminal, which is a substrate voltage terminal of the second MOS transistor circuit, while a gate terminal is connected to the input terminal of the CMOS logic circuit.
According to the above constitution, there is no voltage increase or voltage drop by the threshold voltages of the PMOS transistor and the NMOS transistor generating the switching signal. Thus, the voltage of the switching signal becomes equal to the voltage of the first substrate voltage terminal of the first MOS transistor circuit or the voltage of the second substrate voltage terminal of the second MOS transistor circuit.
In one embodiment of the present invention, the absolute value of the threshold voltage of the p-type MOS transistors generating the switching signal is set to be higher than the difference between a voltage of the first substrate voltage terminal and a voltage of the power supply voltage terminal and lower than the difference between a voltage of the first substrate voltage terminal and a voltage of the ground voltage terminal, and
the absolute value of the threshold voltage of the n-type MOS transistor generating the switching signal is set to be higher than the difference between a voltage of the second substrate voltage terminal and a voltage of the ground voltage terminal and lower than the difference between a voltage of the second substrate voltage terminal and a voltage of the power supply voltage terminal.
According to the above constitution, when the voltage of the input terminal of the CMOS logic circuit becomes equal to the power supply voltage, the PMOS transistor generating the switching signal is turned off while the NMOS transistor is turned on. Thus, the switching signal becomes equal to the voltage of the second substrate voltage terminal. When the voltage of the input terminal becomes equal to the ground voltage, the PMOS transistor is turned on while the NMOS transistor is turned off. Thus, the switching signal becomes equal to the voltage of the first substrate voltage terminal.
In one embodiment of the present invention, the semiconductor substrate or well with which the p-type MOS transistor generating the switching signal is formed is connected to the first substrate voltage terminal, and the semiconductor substrate or well with which the n-type MOS transistor generating the switching signal is formed is connected to the second substrate voltage terminal.
According to the above constitution, the voltage of the substrate or well of the PMOS transistor and the NMOS transistor generating the switching signal becomes equal to the voltage of the source terminal. Therefore, the absolute values of the threshold voltages of the PMOS transistor and the NMOS transistor increase and thereby leakage currents through these MOS transistors are suppressed.
Also, there is provided a latching circuit comprising the CMOS logic circuit.
According to the above constitution, since the CMOS logic circuit constituted by the MOS transistor circuit according to the first aspect of the invention is provided, connections of the semiconductor substrate or well of the MOS transistor constituting the MOS transistor circuit are switched between the gate terminal and the substrate voltage terminal so that leakage currents of the latching circuit are suppressed and thereby lower power consumption is achieved.
Also, there is provided a flip-flop comprising the CMOS logic circuit.
According to the above constitution, since the CMOS logic circuit constituted by the MOS transistor circuit according to the first aspect of the invention is provided, connections of the semiconductor substrate or well of the MOS transistor constituting the MOS transistor circuit are switched between the gate terminal and the substrate voltage terminal so that leakage currents of the flip-flop are suppressed and thereby lower power consumption is achieved.
In one embodiment of the present invention, the CMOS logic circuit is used in the configuration of either the master-stage latching circuit or slave-stage latching circuit.
According to the above constitution, out of the master-stage latching circuit and the slave-stage latching circuit, leakage currents of the one using the CMOS logic circuit are suppressed and thereby lower power consumption is achieved.
Also, there is provided a data storage circuit for once storing data of an operation stopping circuit when power supply is stopped to the operation stopping circuit, wherein the latching circuit is included in the configuration.
According to the above constitution, since the latching circuit or the flip-flop provided with the CMOS logic circuit constituted by the MOS transistor circuit according to the first aspect of the invention is included, leakage currents of the data storage circuit are suppressed and thereby lower power consumption is achieved.
In one embodiment of the present invention, there is provided power supply stopping means for stopping power supply to a latching circuit not using the CMOS logic circuit out of a master-stage latching circuit and a slave-stage latching circuit constituting the flip-flop when power supply is stopped to the operation stopping circuit.
According to the above constitution, out of the master-stage latching circuit and the slave-stage latching circuit constituting the flip-flop, the power supply stopping means stops power supply to the latching circuit which does not include a CMOS logic circuit according to the second aspect of the invention. In this case, leakage currents are suppressed by operation of the MOS transistor circuit according to the first aspect of the invention in the latching circuit which includes the CMOS logic circuit. Thus, leakage currents in the data storage circuit when power supply is stopped are suppressed and thereby lower power consumption is achieved.